BOFFDONEMSK=0, PREXCEN=0, RRS=0, EACEN=0, MRP=0, STFCNTEN=0, TIMER_SRC=0, EDFLTDIS=0
Control 2 register
| EDFLTDIS | Edge Filter Disable 0 (0): Edge Filter is enabled. 1 (1): Edge Filter is disabled. |
| STFCNTEN | Stuff Count Enable 0 (0): Stuff Count feature is disabled. Stuff Count bit field is not inserted before the CRC Sequence field. 1 (1): Stuff Count feature is enabled. Stuff Count bit field is inserted before the CRC Sequence field. |
| PREXCEN | Protocol Exception Enable 0 (0): Protocol Exception is disabled. 1 (1): Protocol Exception is enabled. |
| TIMER_SRC | Timer Source 0 (0): The Free Running Timer is clocked by the CAN bit clock, which defines the baud rate on the CAN bus. 1 (1): The Free Running Timer is clocked by an external time tick. The period can be either adjusted to be equal to the baud rate on the CAN bus, or a different value as required. See the device specific section for details about the external time tick. |
| EACEN | Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes 0 (0): Rx Mailbox filter’s IDE bit is always compared and RTR is never compared despite mask bits. 1 (1): Enables the comparison of both Rx Mailbox filter’s IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. |
| RRS | Remote Request Storing 0 (0): Remote Response Frame is generated. 1 (1): Remote Request Frame is stored. |
| MRP | Mailboxes Reception Priority 0 (0): Matching starts from Rx FIFO and continues on Mailboxes. 1 (1): Matching starts from Mailboxes and continues on Rx FIFO. |
| TASD | Tx Arbitration Start Delay |
| RFFN | Number Of Rx FIFO Filters |
| BOFFDONEMSK | Bus Off Done Interrupt Mask 0 (0): Bus Off Done interrupt disabled. 1 (1): Bus Off Done interrupt enabled. |